Changes
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*Nonblocking STM “steals” ownership of a memory location from another transaction, rather than waiting for the other transaction to explicitly release it. Accessing stolen locations is more complicated and expensive than accessing unstolen ones, but stealing is worthwhile in order to avoid waiting for another transaction that is delayed for a long time.
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====[http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=3&f=G&l=50&co1=AND&d=PTXT&s1=transactional.TI.&s2=memory.TI.&OS=TTL/transactional+AND+TTL/memory&RS=TTL/transactional+AND+TTL/memory Non-blocking conditions]====
==Search strategy==
===English Search concepts==={|border="2" cellspacing="0" cellpadding="4" width="100%" align| style="leftbackground-color:#B6DDE8;padding:0.079cm;"width="4%"| <center>'''S. No.'''</center>|bgcolor style= "background-color:#FFFF99B6DDE8;padding:0.079cm;" width="20%"|<center>'''Transactional memory'''</center>|bgcolor style= "background-color:#FFFF99B6DDE8;padding:0.079cm;" width="20%"|<center>'''Atomic memory transactions'''</center>|bgcolor style= "background-color:#FFFF99B6DDE8;padding:0.079cm;" width="20%"|<center>'''Concurrency control'''</center>|bgcolor style= "background-color:#FFFF99B6DDE8;padding:0.079cm;" width="20%"|<center>'''Shared memory access'''</center>
|-
|transactional style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''1'''</center>| style="padding:0.079cm;"| Transactional memory|atomic style="padding:0.079cm;"| Atomic memory transactions|concurrency style="padding:0.079cm;"| Concurrency control|shared style="padding:0.079cm;"| Shared memory synchronization
|-
|transactional style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''2'''</center>| style="padding:0.079cm;"| Transactional execution AND memory|atomically style="padding:0.079cm;"| Atomically memory accesses|concurrent style="padding:0.079cm;"| Concurrent computing|shared style="padding:0.079cm;"| Shared memory access
|-
|hybrid style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''3'''</center>| style="padding:0.079cm;"| Hybrid transactional memory| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"|
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|software style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''4'''</center>| style="padding:0.079cm;"| Software transactional memory| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"|
|-
|hardware style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''5'''</center>| style="padding:0.079cm;"| Hardware transactional memory| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"| |} === French Search concepts==={|border="2" cellspacing="0" cellpadding="4" width="100%"| style="background-color:#B6DDE8;padding:0.079cm;" width="4%"| <center>'''S. No.'''</center>| style="background-color:#B6DDE8;padding:0.079cm;" width="20%"| <center>'''Transactional memory'''</center>| style="background-color:#B6DDE8;padding:0.079cm;" width="20%"| <center>'''Atomic memory transactions'''</center>| style="background-color:#B6DDE8;padding:0.079cm;" width="20%"| <center>'''Concurrency control'''</center>| style="background-color:#B6DDE8;padding:0.079cm;" width="20%"| <center>'''Shared memory access'''</center>
|-
| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''1'''</center>| style="padding:0.079cm;"| mémoire transactionnelle| style="padding:0.079cm;"| opérations de mémoire atomique| style="padding:0.079cm;"| contrôle de concurrence| style="padding:0.079cm;"| La synchronisation de mémoire partagée |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''2'''</center>| style="padding:0.079cm;"| l'exécution des transactions AND mémoire| style="padding:0.079cm;"| accès à la mémoire atomique| style="padding:0.079cm;"| programmation concurrente| style="padding:0.079cm;"| Accès à la mémoire partagée |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''3'''</center>| style="padding:0.079cm;"| hybride mémoire transactionnelle| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"| |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''4'''</center>| style="padding:0.079cm;"| mémoire logiciel transactionnel| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"| |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''5'''</center>| style="padding:0.079cm;"| mémoire matérielle transactionnel| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"| |} === German Search concepts==={|border="2" cellspacing="0" cellpadding="4" width="100%"| style="background-color:#B6DDE8;padding:0.079cm;" width="4%"| <br clearcenter>'''S. No.'''</center>| style="allbackground-color:#B6DDE8;padding:0.079cm;"width="20%"| <center>'''Transactional memory'''</center>| style="background-color:#B6DDE8;padding:0.079cm;" width="20%"| <center>'''Atomic memory transactions'''</center>| style="background-color:#B6DDE8;padding:0.079cm;" width="20%"| <center>'''Concurrency control'''</center>| style="background-color:#B6DDE8;padding:0.079cm;" width="20%"| <center>'''Shared memory access'''</center> |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''1'''</center>| style="padding:0.079cm;"| transaktionalen Speicher| style="padding:0.079cm;"| Atom-Speicher-Transaktionen| style="padding:0.079cm;"| Concurrency Kontrolle| style="padding:0.079cm;"| Shared-Memory-Synchronisation |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''2'''</center>| style="padding:0.079cm;"| transaktionale Ausführung AND Speicher| style="padding:0.079cm;"| atomar Speicherzugriffe| style="padding:0.079cm;"| Concurrent Computing| style="padding:0.079cm;"| Shared-Memory-Zugriff |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''3'''</center>| style="padding:0.079cm;"| Hybrid transaktionalen Speicher| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"| |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''4'''</center>| style="padding:0.079cm;"| Software transaktionalen Speicher| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"| |-| style="background-color:#B6DDE8;padding:0.079cm;"| <center>'''5'''</center>| style="padding:0.079cm;"| Hardware transaktionalen Speicher| style="padding:0.079cm;"| | style="padding:0.079cm;"| | style="padding:0.079cm;"| |}
===Search strings===
==Top IPC and US Classes==
*'''Top IPC class:''' G06F
[[Image:IPC_class-Transactional_memory.jpg|align|thumb|leftcenter|500px|IPC class]] *'''Top US class:''' 711, 707, 712, 717, 718[[Image:US_class-Transactional_memory.jpg|align|thumb|rightcenter|500px|US class]]
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