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<\/a><\/p>\nFigure 1 ISO 26262 Overview [Source: National Instruments<\/a>]<\/p>\n ISO 26262 standard provides specifications to be followed during development process of automotive SoCs at system, hardware and firmware level. It also serves as a reference for testing process and acceptable risk level to the end-user better known as Automotive Safety Integrity Levels (ASILs).<\/p>\n ISO 26262 defines five classifications of Automotive Safety Integrity Levels (ASILs)<\/a> \u2014 QM, A, B, C, and D \u2014 with ASIL QM offering the basic quality management measures and ASIL D providing the most stringent specification to protect against fatal injuries. The \u00a0safety mechanism technologies relevant to automotive functional safety are error correction code (ECC), hardware duplication of components, fault safety controllers, and built-in self-test (BIST). Implementing ISO 26262 specs on silicon allows a faster response over the software-centric approaches that may become the reason for difference between life and death. It also makes the SoC output more deterministic by reducing the randomness associated with pipelined code execution. Safety management and standardization becomes even more crucial considering the number and diversity of intellectual property (IP) cores being added on an average automotive SoC these days.<\/p>\n The on-chip interconnect plays a vital role in handling diagnostic coverage with interfacing between heterogenous IP cores while maintaining scalability and efficiency. Interconnect IP handles data transfer between different blocks and can help to meet the requirements for ISO 26262 automotive functional safety. Figure 2 below shows one such example of Interconnect IP used for on-chip communication on cache-coherent ICs used in autonomous driving, AI\/ML applications and automotive sensor fusion.<\/p>\n Figure 2 Interconnect IP with multi-IP support [Source: Arteris<\/a>]<\/p>\n With the slowdown of Moore\u2019s law limiting the exponential increase in integration density and diminishing returns on investment in fabs with feature size below 10 nm, alternative system architectures are competing for system architect\u2019s attention. One of them is the chiplet approach which allows prefabricated circuits to be assembled on silicon and interconnected using Standard Interconnect IP. Chiplet approach<\/a> is more suitable for developers of autonomous vehicles which are being developed in multiple phases. While mid-class vehicles only permit partially autonomous driving, high end vehicles offer full array of autonomous functionalities. This requires different levels of processing power and interfaces that can be implemented on single silicon and connected using a standard Interconnect network.<\/p>\n Assessment of technical and commercial feasibility of design IPs need to be made in advance before committing huge amount of resources into their development. White space analysis and patentability searches can play a vital role in preventing firms from reinventing the wheel. In-house experts of Dolcera have proven it time and again that they are capable of generating good quality reports with detailed patent and market analysis in multi-disciplinary domains ranging from smart drug delivery systems<\/a> to hybrid electric vehicles<\/a> and everything in between. Figure 3 below shows snapshot of the report on Hybrid Electric Vehicles delivered by Dolcera using AI enabled patent analytics engine Patent Categorization System (PCS).<\/p>\n Figure 3 Snapshot of Dolcera’s report on Hybrid Vehicles<\/a><\/p>\n PCS is Dolcera\u2019s flagship patent analytics platform. With a corpus of over 110 million worldwide patents updated daily, PCS provides answers to every patent question in detail and blindingly fast.<\/p>\n For more queries, feel free to visit us at http:\/\/dolcera.com\/<\/a><\/p>\n<\/a><\/p>\n<\/a><\/p>\n