Transactional memory in hardware

Contents

Background

Transactional memory

More details


Transactional programming models


Software based Transactional memory

DracoSTM


Dynamic STM (DSTM)

Dynamic Software Transactional Memory 2.0 (DSTM2)

Nonblocking Software Transactional Memory

Like this report?

This is only a sample report with brief analysis
Dolcera can provide a comprehensive report customized to your needs

Buy the customized report from Dolcera
Patent Analytics Services Market Research Services Purchase Patent Dashboard
Patent Landscape Services Dolcera Processes Industry Focus
Patent Search Services Patent Alerting Services Dolcera Tools


Non-blocking conditions

Lock-free transactional memory
Wait-free transactional memory
Obstruction-free transactional memory

Hardware based Transactional memory

Adaptive Transactional Memory Test Platform

Unbounded Hardware Transactional Memory (UHTM)

Best-effort Hardware Transactional Memory

Split Hardware Transaction (SpHT)

Virtualized Transactional Memory (VTM)

Conflict detection

Hybrid Transactional memory (HyTM)

Phased Transactional Memory (PhTM)

Nonblocking Zero-Indirection Transactional Memory (NZTM)

Hardware-Accelerated STM (HASTM)

Signature-Accelerated STM (SigTM)



Search strategy

English Search concepts

S. No.
Transactional memory
Atomic memory transactions
Concurrency control
Shared memory access
1
Transactional memory Atomic memory transactions Concurrency control Shared memory synchronization
2
Transactional execution AND memory Atomically memory accesses Concurrent computing Shared memory access
3
Hybrid transactional memory
4
Software transactional memory
5
Hardware transactional memory

French Search concepts

S. No.
Transactional memory
Atomic memory transactions
Concurrency control
Shared memory access
1
mémoire transactionnelle opérations de mémoire atomique contrôle de concurrence La synchronisation de mémoire partagée
2
l'exécution des transactions AND mémoire accès à la mémoire atomique programmation concurrente Accès à la mémoire partagée
3
hybride mémoire transactionnelle
4
mémoire logiciel transactionnel
5
mémoire matérielle transactionnel

German Search concepts

S. No.
Transactional memory
Atomic memory transactions
Concurrency control
Shared memory access
1
transaktionalen Speicher Atom-Speicher-Transaktionen Concurrency Kontrolle Shared-Memory-Synchronisation
2
transaktionale Ausführung AND Speicher atomar Speicherzugriffe Concurrent Computing Shared-Memory-Zugriff
3
Hybrid transaktionalen Speicher
4
Software transaktionalen Speicher
5
Hardware transaktionalen Speicher


Search strings

Concepts Scope Search string No of hits
Transactional memory Search scope: US Granted US Applications EP-A EP-B WO JP DE-C,B DE-A DE-T DE-U GB-A FR-A;
Claims, Title or Abstract
Years: 1836-2008
(transactional ADJ memory) OR ((transactional ADJ execution) SAME memory) 167
Other Keywords (atomic*4 NEAR2 memory NEAR2 (transaction*1 OR access*2)) OR (((concurrency ADJ control) OR (concurrent ADJ computing)) WITH ((shared ADJ memory) AND (synchronization OR access*2))) 24
Final 1 OR 2 82 unique (189 patents including families)


IP Trend

Year wise graph

Key companies

Top Assignees

Top IPC and US Classes

IPC class
US class



Sample analysis

S.No. Patent/Publication No. Title Transactional memory Summary
1 US20040015642A1 Software transactional memory for dynamically sizable shared data structures Dynamic STM (DSTM) A software transactional memory that allows concurrent non-blocking access to a dynamically sizable data structure defined in shared storage managed by the software transactional memory is described. The implementation is called dynamic software transactional memory (DSTM). DSTM techniques allow transactions and transactional objects to be created dynamically. The non-blocking property considered here is obstruction-freedom.
2 US20060085591A1 Hybrid hardware and software implementation of transactional memory access Phased Transactional Memory (PhTM) The invention relates to a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.
3 US20070028056A1 Direct-update software transactional memory Dynamic STM (DSTM) A transactional memory programming interface allows a thread to directly and safely access one or more shared memory locations within a transaction while maintaining control structures to manage memory accesses to those same locations by one or more other concurrent threads. Each memory location accessed by the thread is associated with an enlistment record, and each thread maintains a transaction log of its memory accesses.
4 US20070156780A1 Protecting shared variables in a software transactional memory system Dynamic STM (DSTM) For a variable accessed at least once in a software-based transactional memory system (STM) defined (STM-defined) critical region of a program, modifying an access to the variable that occurs outside any STM-defined critical region system by starting a hardware based transactional memory based transaction, within the hardware based transactional memory based transaction, checking if the variable is currently owned by a STM transaction, If the variable is not currently owned by a STM transaction, performing the access and then committing the hardware based transactional memory transaction and if the variable is currently owned by a STM transaction, performing a responsive action.
5 US20070156994A1 Unbounded transactional memory systems Unbounded Hardware Transactional Memory (UHTM) Methods and apparatus to provide unbounded transactional memory systems are described. Transactional memory is implemented through a table lookup mechanism. To access a shared resource, a thread may first check a table stored in memory to determine whether another thread is accessing the same portion of the shared resource. Accessing a table that is stored in memory may generate overhead that decreases performance.
6 US20070239942A1 Transactional memory virtualization Virtualized Transactional Memory (VTM) Methods and apparatus to provide transactional memory execution in a virtualized mode are described. Data corresponding to a transactional memory access request is stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.
7 US20070300238A1 Adapting software programs to operate in software transactional memory environments Dynamic Software Transactional Memory 2.0 (DSTM2) Software transactional memory is used in non-managed language environments and with legacy codes without requiring a software programmer to change the programming paradigm they are currently used to. STM adapter system automatically transforms all the binary code executed within that block to execute atomically. STM adapter system automatically transforms lock-based critical sections in existing binary code to atomic blocks,
8 US20080005504A1 Global overflow method for virtualized transactional memory Virtualized Transactional Memory (VTM) A method and apparatus for virtualizing and/or extending transactional memory is described. Transactions are executed using local shared transactional memory, such as a cache memory. Upon overflowing the shared transactional memory, the transactional memory is virtualized and/or extended into a higher-level memory, such as a system memory.
9 US20080098374A1 Method and apparatus for performing dynamic optimization for software transactional memory Dynamic STM (DSTM) The present invention relates to a method and apparatus for performing dynamic optimization for STM. An optimistically immutable field is determined in the transaction to write. The transaction optimization unit keeps track of the status of object and class fields in a transaction. The transaction optimization unit invalidates methods corresponding to an optimistically immutable field in response to determining that the field has been written to and is therefore not immutable.
10 WO2008088931A2 FACILITATING EFFICIENT TRANSACTIONAL MEMORY AND ATOMIC OPERATIONS VIA CACHE LINE MARKING Hardware-Accelerated STM (HASTM)-Conflict detection The system starts by executing a transaction for a thread, wherein executing the transaction involves placing load-marks on cache lines which are loaded during the transaction and placing store-marks on cache lines which are stored to during the transaction. Upon completing the transaction, the system releases the load-marks and the store-marks from the cache lines which were load-marked and store-marked during the transaction. Note that during the transaction, the load-marks and store-marks prevent interfering accesses from other threads to the cache lines.



Patent dashboard

Patent Categorization in Dashboard

Like this report?

This is only a sample report with brief analysis
Dolcera can provide a comprehensive report customized to your needs

Buy the customized report from Dolcera
Patent Analytics Services Market Research Services Purchase Patent Dashboard
Patent Landscape Services Dolcera Processes Industry Focus
Patent Search Services Patent Alerting Services Dolcera Tools


Contact Dolcera

Samir Raiyani
Email: info@dolcera.com
Phone: +1-650-269-7952